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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:53:02 01/21/2010 
-- Design Name: 
-- Module Name:    SimpleSOC - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- General package
use work.GeneralProperties.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SimpleSOC is
    Port ( CLK : in  STD_LOGIC;
           RESET : in  STD_LOGIC;
			  RUN          : out  STD_LOGIC;			  
           STATUS_LED : out  STD_LOGIC_VECTOR((bus_size-1) downto 0));
end SimpleSOC;

architecture Behavioral of SimpleSOC is
  
  component SimpleProcessor is
    Port ( RESET : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           External : inout  STD_LOGIC_VECTOR   ((bus_size-1) downto 0);
           MEM_WriteAdd : out  STD_LOGIC_VECTOR ((bus_size-1) downto 0);
           MEM_ReadAdd : out  STD_LOGIC_VECTOR  ((bus_size-1) downto 0);
           MEM_Read : out  STD_LOGIC;
           MEM_Write : out  STD_LOGIC;			  
			  RUN          : out  STD_LOGIC;			  
			  MEM_Data_out : out  STD_LOGIC_VECTOR ((bus_size-1) downto 0);
           MEM_Data : in  STD_LOGIC_VECTOR ((bus_size-1) downto 0));
  end component;
  
  component MemorySample is
  Port (
    CLK                  : in     STD_LOGIC;
	 MEM_Data             : out    STD_LOGIC_VECTOR ((bus_size-1) downto 0);
    MEM_DataIn           : in     STD_LOGIC_VECTOR ((bus_size-1) downto 0);
	 MEM_WriteAdd         : in     STD_LOGIC_VECTOR ((bus_size-1) downto 0);
	 MEM_ReadAdd          : in     STD_LOGIC_VECTOR  ((bus_size-1) downto 0);
    MEM_Read             : in     STD_LOGIC;	 
    MEM_Write            : in     STD_LOGIC
  );
  end component;
  signal MEM_Data             : STD_LOGIC_VECTOR ((bus_size-1) downto 0);
  signal MEM_Data_out         : STD_LOGIC_VECTOR ((bus_size-1) downto 0);
  signal MEM_DataIn           : STD_LOGIC_VECTOR ((bus_size-1) downto 0);
  signal MEM_WriteAdd         : STD_LOGIC_VECTOR ((bus_size-1) downto 0);
  signal MEM_ReadAdd          : STD_LOGIC_VECTOR  ((bus_size-1) downto 0);
  signal MEM_Read             : STD_LOGIC;
  signal MEM_Write            : STD_LOGIC;
  signal MEM_Enable           : STD_LOGIC;
  signal External             : STD_LOGIC_VECTOR   ((bus_size-1) downto 0);
begin
  Processor : SimpleProcessor port map (RESET,CLK,External,MEM_WriteAdd,MEM_ReadAdd,MEM_Read,MEM_Write,RUN,MEM_Data_out,MEM_Data);
  Memory    : MemorySample port map (CLK,MEM_Data,MEM_Data_out,MEM_WriteAdd,MEM_ReadAdd,MEM_Read,MEM_Write);
  
  STATUS_LED <= External;

end Behavioral;

